Challenges Ahead

As the critical dimension shrinks to 65nm and below, designers and foundries are facing new challenges together. More complicated design rules come frequently from the foundary due to manufacture process variations; while at the same time, more design rule violations arise from the layout due to design complexity, SoC integration, layout migration or shrinking, and limited capability of traditional P&R tool to handle all design rules. Furthermore, model-based layout analysis emerges among foundries and designers to ensure acceptable chip yield, which detects layout problem that just can't be fully covered by design rule check. The real challenge remains how to fix all these layout violations, either design rule violation or model-based hotspot, without hampering chip performance and delaying the already tightened tapeout schedule.

Nannor's Approach